Supported by the National Natural Science Foundation of China (Grant No. T2588301), Professor Hailin Peng’s group from Peking University and their collaborators have developed a novel high-dielectric-constant (κ) van der Waals ferroelectric material, α-bismuth selenite (Bi₂SeO₅). They fabricated ferroelectric transistors and logic-in-memory circuits operating at an ultralow voltage (0.8 V) with extremely high endurance (>1.5×10¹² cycles). The exceptional performance significantly surpasses that of the existing industrial-grade hafnium-based ferroelectric systems. The related findings were published in  Science  on January 29, 2026, entitled "Wafer-scale ultrathin and uniform van der Waals ferroelectric oxide." The paper link is: http://dx.doi.org/10.1126/science.adz1655.

In the era of artificial intelligence (AI), ferroelectric materials with fast polarization switching characteristics offer opportunities for developing computing-in-memory architectures to break through the existing "power consumption wall" and "memory wall" of conventional architectures. Among them, ferroelectric field-effect transistors (FeFETs), which integrate logic and memory functions, are regarded as core devices for constructing next-generation high-efficiency embedded memories and compute-in-memory chips. Currently, the preparation of wafer-scale uniform and ultrathin ferroelectric films is a key challenge limiting the practical application of ferroelectric devices. How to maintain ferroelectricity at the atomic-layer thickness and achieve reliable, consistent wafer-scale integration has become a core problem that must be overcome for developing high-efficiency ferroelectric compute-in-memory chips.

To address the above issues, the research team developed the novel bismuth-based two-dimensional ferroelectric material α-Bi₂SeO₅. They established a back-end-of-line (BEOL) compatible (≤400 °C) in-situ oxidation preparation method, achieving for the first time the controllable preparation of wafer-scale, ultrathin, uniform ferroelectric films and ferroelectric/semiconductor heterostructures. Based on this material system, the team successfully fabricated high-performance ferroelectric transistors. Under ultra-low voltage (0.8 V) and high-speed writing (20 ns) conditions, the devices demonstrated endurance exceeding 1.5×10¹² cycles, along with a retention time of 10 years, 5-bit multi-level storage capability, and ultra-low energy consumption of 2.8 fJ bit⁻¹ μm⁻². This performance has already surpassed the industry's highest level for devices of the same type. Furthermore, the constructed dynamically reconfigurable in-memory logic computing circuits can achieve reconfigurable logic functions under conventional CMOS-compatible operating voltages (<1 V). This work simultaneously breaks through the limits in both ferroelectric material preparation and ferroelectric device performance, providing a novel material platform and integration scheme for next-generation high-performance, low-power chip technology. It marks an important leap from material innovation to functional verification in the "More than Moore" roadmap.

Figure: Wafer-scale two-dimensional high-κ ferroelectric oxide system and high-performance ferroelectric transistor.