Chinese Scholars Made Progress in Wafer-scale Synthesis of Ultrathin Sapphire
With support from the National Natural Science Foundation of China (Grant Nos. 51925208, 62122082) and other funding sources, the research team led by Zengfeng Di at the Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, has made progress in developing single-crystal metal oxide gate dielectric wafers for low-power two-dimensional integrated circuits. The research results were published online in Nature on August 7, 2024, titled "Single-crystalline metal-oxide dielectrics for top-gate 2D transistors" (Paper link: https://www.nature.com/articles/s41586-024-07786-2).
Two-dimensional semiconductor materials, with advantages such as high carrier mobility and suppression of short-channel effects, are ideal channel materials for next-generation electronics, and could enable further miniaturization of transistors. However, the lack of high-quality gate dielectric materials matching these 2D semiconductor channel materials leads to significant discrepancies between the actual and theoretical performance of 2D transistors. Traditional silicon-based amorphous gate dielectrics suffer from a high density of dangling bonds on their surface. These bonds, when in contact with 2D semiconductor materials, create interface states that act as electron traps, significantly degrading 2D transistor performance. Single-crystal gate dielectric materials can form perfect interfaces with 2D semiconductor channel materials, but their growth usually requires high process temperatures and post-annealing treatments, which can easily damage or unintentionally dope 2D semiconductor materials, forming non-ideal gate dielectric/2D semiconductor interfaces. As a result, the interface state density is typically as high as 1011 cm-2 eV-1, failing to meet the requirements for future advanced low-power chips.
The research team led by Zengfeng Di developed a novel single-crystal metal intercalation oxidation technique. This method enables the fabrication of single-crystal aluminum oxide (c-Al2O3) gate dielectric wafers at room temperature, which they subsequently applied to the development of advanced low-power 2D integrated circuits. The research team employed graphene-coated germanium wafers as substrates for the epitaxial growth of single-crystal aluminum (Al) with a (111) crystallographic orientation. Exploiting the weak van der Waals force between graphene and Al, they achieved non-destructive exfoliation of 4-inch single-crystal Al (111) wafers from graphene/Ge substrate (Figure). The exfoliated Al (111) surface exhibited atomic-level smoothness without defects. Under extremely low oxygen environment, oxygen atoms are controllably inserted layer by layer into the lattice of the single-crystal Al (111) surface while maintaining its lattice structure. By using this technique, a stable, stoichiometric and atomically thin c-Al2O3 layer with a thickness of 1.25 nm is formed on the Al surface at room temperature. Furthermore, using a self-aligned process, they successfully fabricated low-power c-Al2O3/MoS2 transistor arrays. These transistors demonstrated a breakdown field strength of 17.4 MV cm-1, gate leakage current of 10-6 A cm-2, and interface state density of 8.4×109 cm-2 eV-1, meeting the International Roadmap for Devices and Systems (IRDS) requirements for future low-power integrated circuits.
This research demonstrates the possibility of producing high-quality single-crystal oxides as gate dielectric materials, providing a potential gate dielectric solution for the development of advanced 2D transistors.
Figure. a) Schematic illustration of c-Al2O3 formation through single-crystalline Al intercalation oxidation technique; b) 4-inch single-crystalline Al (111) wafer; c) Cross-sectional HRTEM image of single-crystalline Al (111)/c-Al2O3 on SiO2 substrate. Scale bar: 1 nm; d) Thicknesses mapping of the c-Al2O3 wafer.
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